S6J32DA Datasheet, PDF (177/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo Family

S6J3200 Series
Summary
Error
Correct
ID
Display AC
132
specification
Display AC
133
specification
FPD-Link Output
135
Clock Frequency
Add "TxCLK+/-" in
case of don't
135
support FPD-Link
DDRHSSPI (SDR)
clock cycle for
138
Quad Page
Program
HyperBus AC
144
specification
ADC Software
153
Trimming
-
132
-
133
Output clock frequency:
135
1MHz(min),50MHz(max)
Note: − All the corresponding ports of
products which don't support FPD-Link
should be connected to GND.
135
AVCC3_LVDS_PLL, AVSS3_LVDS_PLL,
VCC3_LVDS_Tx, VSS3_LVDS_Tx,
TxDOUTn+/-.
-
138
RDS↑↓> DQ (valid) Setup time ,,,
144
RDS↑↓> DQ (invalid)Hold time
-
153
( - Updated the min/max value for |tRSD|,
tRSV, tSPD, tSPV. - Delete the note for
#506
*2. - Updated figure for definition of tSPV
and tRSV.)
( - Updated the min/max value for tDC1D,
tDC1V and delete the remarks for tDC1V. #505
- Updated figure for definition of tDC1V.)
Output clock frequency: -
(min),50MHz(max)
#522
Note: − All the corresponding ports of
products which don't support FPD-Link
should be connected to GND.
#525
AVCC3_LVDS_PLL, AVSS3_LVDS_PLL,
VCC3_LVDS_Tx, VSS3_LVDS_Tx,
TxDOUTn+/-, TxCLK+/-.
HSSPI clock cycle:20(Min):when Quad
#484
Page Program
RDS↑↓> DQ Setup time ,,,
RDS↑↓> DQ Hold time
8.5.4 Calibration ConditionCalibration
Condition A/D Converter should be
calibrated under the following
condition.AVCC=5.0V AVRH=5.0V
Ta=25℃ system clock frequency
(CLK_LCP1A)= 10MHz See A/D
Converter Calibration on the S6J3200
hardware manual.
#519
#358
Document Number: 002-05682 Rev.*A
Page 177 of 179