S6J32DA Datasheet, PDF (170/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo Family

S6J3200 Series
Summary
Error
Correct
ID
Hardware flow
18
control
Pin assignment
and pin list should
be separately
20
instead of the red
characters
DDR-HSSPI DDR
110
Mode
Multi-functional Serial (MFS):,,,
Multi-functional Serial (MFS):CTS/RTS is
20
not mounted (hardware flow control is not #373
supported for this series.)
-
24-37 (The figure of pin assignment are added) #374
Note:
,,,
140
- SS2CD [1:0] should be configured as 01,
10, or 10.
Notes:
,,,
#376
- SS2CD [1:0] should be configured as 01,
10, or 11.
Oscillator Error
76
Issue
Notes:− *1: Target maximum clock
100
frequencies when CPU clock = 240MHz- ,,,
Notes:− *1: Target maximum clock
frequencies when CPU clock = 240MHz -
232MHz or less is available for SSCG #380
Down Spread. - 240MHz or less is
available for PLL.- ,,,
Input Pulse Width 120
Port Noise Filter:
Width for input removal: All GPIO:
25ns(max)
151
*: Input pulse width less than at least 25nm
is removed when Port noise filter is enabled.
Port Noise Filter:
Width for input removal: All GPIO:
67ns(max)
*: Input pulse width less than at least Typ
#382
25ns to Max 67ns is removed when Port
noise filter is enabled.
*: Input pulse width 100ns or more is
recommended to be effective.
TYPO in 216 pin
assign
21,22
P0_26 0
P0_27 0
P0_28 0
24-30
("0"s are removed)
P0_26
P0_27
P0_28
#384
CHIP ID
12
-
RVD
Detection/Release 99
-
Voltage
DDH-HSSPI AC 109,
Specification
110
(Old value)
HyperBus AC
Specification
111-11
(Old value)
4
Function Digit: 3,4,5,6,7,8
E and F:
Chip ID: 0x10100101, JTAG ID:
0x1000C5CF
14
---
Function Digit: A,B,C,D
E and F:
Chip ID: 0x10110001, JTAG ID:
0x100095CF
124 (LVDL0 spec is added.)
138,
(New values are added in the table)
140
142-14
(New values are added in the table)
5
#409
#410
#411
#412
Document Number: 002-05682 Rev.*A
Page 170 of 179