CY8CLED04D01 Datasheet, PDF (17/52 Pages) Cypress Semiconductor – PowerPSoC Intelligent LED Driver

CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
10. Designing with User Modules
The development process for the PowerPSoC device differs
from that of a traditional fixed function microprocessor. The
configurable power, analog, and digital hardware blocks give the
PowerPSoC architecture a unique flexibility that pays dividends
in managing specification change during development and by
lowering inventory costs. These configurable resources, called
PowerPSoC Blocks, have the ability to implement a wide variety
of user selectable functions. The PowerPSOC development
process can be summarized in the following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify and Debug
Select Components. In the chip-level view the components are
called “user modules”. User modules make selecting and imple-
menting peripheral devices simple and come in power, analog,
digital, and mixed signal varieties. The standard user module
library contains over 50 common peripherals such as Current
Sense Amplifiers, PrISM, PWM, DMM, Floating Buck, Boost,
ADCs, DACs, Timers, Counters, UARTs, and other not so
common peripherals such as DTMF generators and Bi-Quad
analog filter sections.
Configure Components. Each of the components selected
establishes the basic register settings that implement the
selected function. They also provide parameters allowing
precise configuration to your particular application. For example,
a PWM User Module configures one or more digital PSoC
blocks, one for each 8 bits of resolution. Configure the param-
eters and properties to correspond to your chosen application.
Enter values directly or by selecting values from drop-down
menus.
The chip-level user modules are documented in data sheets that
are viewed directly in PSoC Designer. These data sheets explain
the internal operation of the component and provide perfor-
mance specifications. Each data sheet describes the use of each
user module parameter and other information needed to
successfully implement your design.
Organize and Connect. Signal chains can be built at the chip
level by interconnecting user modules to each other and the IO
pins. In the chip-level view, perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug. When ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high level user
module API functions.
The chip-level designs generate software based on your design.
The chip-level view provides application programming interfaces
(APIs) with high level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows development
and customization of your applications in C, assembly language,
or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
11. Document Conventions
11.1 Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym
AC
ADC
API
CPU
CSA
CT
DAC
DALI
DC
DMM
DMX
DSM
DTMF
ECO
EEPROM
EMI
FAQ
FET
FSR
GPIO
GUI
HBM
IC
ICE
IDE
ILO
IMO
ISSP
I/O
IPOR
LED
Description
Alternating Current
Analog-to-Digital Converter
Application Programming Interface
Central Processing Unit
Current Sense Amplifier
Continuous Time
Digital-to-Analog Converter
Digital Addressable Lighting Interface
Direct Current
Delta Sigma Modulation Mode
Digital Multiplexing
Delta Sigma Modulator
Dual-Tone Multi Frequency
External Crystal Oscillator
Electrically Erasable Programmable Read-Only
Memory
ElectroMagnetic Interference
Frequently Asked Questions
Field Effect Transistor
Full Scale Range
General Purpose IO
Graphical User Interface
Human Body Model
Integrated Circuit
In-Circuit Emulator
Integrated Development Environment
Internal Low-speed Oscillator
Internal Main Oscillator
In-System Serial Programming
Input/Output
Imprecise Power On Reset
Light Emitting Diode
Document Number: 001-46319 Rev. *G
Page 17 of 52
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