CY7C64013C_11 Datasheet, PDF (17/53 Pages) Cypress Semiconductor – Full-Speed USB (12-Mbps) Function

CY7C64013C
CY7C64113C
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register (Table 4 on page 15 through
Table 7 on page 16) and by its associated Port Configuration bits
as shown in the GPIO Configuration Register
(Table 8 on page 16). These ports are configured on a per-port
basis, so all pins in a given port are configured together. The
possible port configurations are detailed in Table 9. As shown in
this table below, when a GPIO port is configured with CMOS
outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register
are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
Table 9. GPIO Port Output Control Truth Table and Interrupt Polarity
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
1
1
0
Output LOW
0
1
Resistive
1
1
0
0
Output LOW
0
1
Output HIGH
1
0
1
0
Output LOW
0
1
Hi-Z
1
0
0
0
Output LOW
0
1
Hi-Z
1
Interrupt Polarity
Disabled
– (Falling Edge)
Disabled
Disabled
Disabled
– (Falling Edge)
Disabled
+ (Rising Edge)
Q1, Q2, and Q3 discussed below are the transistors referenced
in Figure 3 on page 15. The available GPIO drive strength are:
■ Output LOW Mode: The pin’s Data Register is set to ‘0’
Writing ‘0’ to the pin’s Data Register puts the pin in output
LOW mode, regardless of the contents of the Port
Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3
is ON. The GPIO pin is driven LOW through Q3.
■ Output HIGH Mode: The pin’s Data Register is set to 1 and the
Port Configuration Bits[1:0] is set to ‘10’
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is
pulled up through Q2. The GPIO pin is capable of sourcing of
current.
■ Resistive Mode: The pin’s Data Register is set to 1 and the Port
Configuration Bits[1:0] is set to ‘11’
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14 kresistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic
HIGH if the pin is not driven LOW by an external source.
■ Hi-Z Mode: The pin’s Data Register is set to1 and Port
Configuration Bits[1:0] is set either ‘00’ or ‘01’
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven
internally. In this mode, the pin may serve as an input.
Reading the Port Data Register returns the actual logic value
on the port pins.
GPIO Interrupt Enable Ports
Each GPIO pin can be individually enabled or disabled as an
interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin. When
HAPI mode (discussed in Hardware Assisted Parallel Interface
(HAPI) on page 24) is enabled the GPIO interrupts are blocked,
including ports not used by HAPI, so GPIO pins cannot be used
as interrupt sources.
During a reset, GPIO interrupts are disabled by clearing all of the
GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input
pin. All GPIO pins share a common interrupt, as discussed in
GPIO/HAPI Interrupt on page 29.
Table 10. Port 0 Interrupt Enable
Port 0 Interrupt
Enable
ADDRESS 0x04
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0.7 Intr Enable P0.6 Intr Enable P0.5 Intr Enable P0.4 Intr Enable P0.3 Intr Enable P0.2 Intr Enable P0.1 Intr Enable P0.0 Intr Enable
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Table 11. Port 1 Interrupt Enable
Port 1 Interrupt
Enable
Bit #
Bit Name
Read/Write
Reset
7
6
5
4
P1.7 Intr Enable P1.6 Intr Enable P1.5 Intr Enable P1.4 Intr Enable
W
W
W
W
0
0
0
0
3
P1.3 Intr Enabl
W
0
ADDRESS 0x05
2
1
0
P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable
W
W
W
0
0
0
Document Number: 38-08001 Rev. *D
Page 17 of 53
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