CY2SSTU32866 Datasheet, PDF (17/26 Pages) SpectraLinear Inc – 1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity

PRELIMINARY
CY2SSTU32866
C0 = 1, C1 = 1 (RESET switches from H to L)
RESET
DCS†
tinact _{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
CSR†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CLK†
CLK†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D1−D14†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tRPHL
RESET to Q
Q1−Q14
PAR_IN†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tRPHL
RESET to PPO
PPO
(not used)
QERR
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ_{H, L, or X}
tRPLH
RESET to QERR
H or L
Figure 12. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from H to L
Document #: 38-07690 Rev. **
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