CY2SSTU32866 Datasheet, PDF (16/26 Pages) SpectraLinear Inc – 1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity

PRELIMINARY
CY2SSTU32866
RESET
DCS^{ÇÇÇÇÇÇ}
CCCSLLRKK_{ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ}
n
n+1
n+2
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ _D1−D14
tsu
tpdm, tpdmss
th
CLK to Q
Q1−Q14^{ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ}
PAR_IN^{ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ tsu}
th
(noQtEuPsRPeRdO^{†ÉÉÉÉÉÉ}) ^{ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉDDaLtaaaÉÉÉÉÉÉ}_{ttateontoPcyPQCOELRKRto}
tpd
PPO
Latency
ÇÇÇÇÇÇÇÇUnknown input
event
ÉÉÉÉÉÉÉÉ Output signal is dependent on
the prior unknown input event
n+3
n+4
tPHL or tPLH
CLK to QERR
H or L
Figure 11. CY2SSTU32866 used as pair, C0=1, C1=1, RST# being held high
Document #: 38-07690 Rev. **
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