CY28341 Datasheet, PDF (17/21 Pages) Cypress Semiconductor – Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28341
S1
D elay 0 .2 5m S
S2
S a m ple
In p u ts
F S (3:0)
W a it fo r
1 .1 46 m s
E n a b le
O utpu te s
V D D A = 2.0V
S0
P ow er O ff
V D D 3 .3 = O ff
S3
N orm al
O p e ra tio n
Figure 7. Clock Generator Power-up/ Run State Diagram (with P4 Processor SELP4_K7# = 1)
Connection Circuit DDRT/C Signals
For Open Drain CPU Output Signals (with K7 Processor SELP4_K7# = 0)
3.3V
VDDCPU(1.5V)
47 Ohm
CPUOD_T
52 Ohm 5"
60.4 Ohm
52 Ohm 1"
680 pF
301 Ohm
500 Ohm
500 Ohm ^{Measurement Point}
20 pF
47 Ohm
CPUOD_C
52 Ohm 5"
680 pF
60.4 Ohm
3.3V
VDDCPU(1.5V)
52 Ohm 1"
500 Ohm
Measurement Point
500 Ohm
20 pF
Figure 8.
6”
6”
Figure 9.
Document #: 38-07367 Rev. *A
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