CY28341 Datasheet, PDF (14/21 Pages) Cypress Semiconductor – Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28341
Rise and Fall Times
Power-down Deassertion (P4 Mode)
The power-up latency needs to be less than 3 mS.
PW RDW N#
<1.5 m sec
CPU 133MHz
CPU# 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
SDRAM 133MHz
Figure 3. Power-down Deassertion Timing Waveform (in P4 Mode)
AMD K7 Processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) LOW, the device
transitions to a shutdown (power-down) mode and all power
supplies may then be removed. When PD# is sampled LOW
by two consecutive rising edges of CPU clock, then all affected
clocks are stopped in a LOW state as soon as possible. When
in power-down (and before power is removed), all outputs are
synchronously stopped in a LOW state (see figure3 below), all
PLL’s are shut off, and the crystal oscillator is disabled. When
the device is shutdown, the I2C function is also disabled.
Document #: 38-07367 Rev. *A
Page 14 of 21