S6J324C Datasheet, PDF (163/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo Family

S6J3200 Series
Summary
Error
Correct
ID
DC
characterization of 68
PSS
Current
68
consumption
Oscillator
71
frequency range
PLL/SSCG
maximum
73
frequency
Minimum
PLL/SSCG
74
frequency
CAN clock
74
frequency
ICCT5: Timer mode
ICCH5: Stop mode
70
Notes:
- ,,,
Icc12 -(typ) 1700mA(max):CPU:160MHz,
70
HPM:80MHz, GDC:160MHz
Source oscillation clock frequency: X0, X1:
3.6MHz(min), 4.0MHz(max)
73
Notes:
,,,
-
Note:
- ,,,
- ,,,
75, 76
76
ICCT5: PSS Timer mode Shutdown
(PD6=OFF)
ICCH5: PSS Stop mode Shutdown
Notes:
- ,,,
- The definition of timer mode and stop
mode can be seen at the chapter of
STATE transition of S6J3200 hardware
manual.
Icc12 900(typ)
1700mA(max):CPU:160MHz,
HPM:80MHz, GDC:160MHz
Source oscillation clock frequency: X0,
X1:
3.6MHz(min), 16MHz(max)
#214
#260
Notes:
#230
,,,
− Enough evaluation and adjustment are
recommended using oscillator on your
system board.
FSSCG0:480,800(400),640,640 MHz,
SSCG0 output
clockFSSCG1:800(400),800(400),
800(400),800(400) MHz, SSCG1 output
clockFSSCG2:800(400),800(400),
800(400),640 MHz, SSCG2 output
clockFSSCG3:800,800,800,800 MHz,
SSCG3 output
clockFPLL0:720,800,800,640 MHz, PLL0 #208
output clockFPLL1:800,800,800,640
MHz, PLL1 output
clockFPLL2:800(400),800(400),800(400),
800 MHz, PLL2 output
clockFPLL3:480,480,480,480 MHz, PLL3
output clockNotes:- ,,,,− The frequency
described in () is not maximum value but
recommended configuration value.
Note:
- ,,,
- ,,,
#219
− The configurable minimum frequency of
PLLn and SSCGn output is 400MHz.
-
76
FCLK_CAN 40MHz(Max)
#222
Document Number: 002-05682 Rev.*A
Page 163 of 179