CYP15G0401DXB Datasheet, PDF (16/53 Pages) Cypress Semiconductor – Quad HOTLink II Transceiver

CYP15G0401DXB
CYV15G0401DXB
Table 1. Input Register Bit Assignments ^[6]
Signal Name
TXDx[0] (LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
SCSEL
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
N/A
Encoded
2-bit
Control
3-bit
Control
TXDx[0] TXDx[0]
TXDx[1] TXDx[1]
TXDx[2] TXDx[2]
TXDx[3] TXDx[3]
TXDx[4] TXDx[4]
TXDx[5] TXDx[5]
TXDx[6] TXDx[6]
TXDx[7] TXDx[7]
TXCTx[0] TXCTx[0]
TXCTx[1] TXCTx[1]
N/A
SCSEL
Phase-align Buffer
Data from the Input Registers are passed either to the Encoder
or to the associated Phase-align Buffer. When the transmit
paths are operated synchronous to REFCLK (TXCKSEL
= LOW and TXRATE = LOW), the Phase-align Buffers are
bypassed and data is passed directly to the Parity Check and
Encoder blocks to reduce latency.
When an Input-Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL LOW) or if
data is captured on both edges of REFCLK (TXRATE = HIGH),
the Phase-align Buffers are enabled. These buffers are used
to absorb clock phase differences between the presently
selected input clock and the internal character clock.
Initialization of the Phase-align Buffers takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK is set. TXRST is an
asynchronous input, but is sampled internally to synchronize
it to the internal transmit path state machines.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK;
i.e., 180°. This time shift allows the delay paths of the
character clocks (relative to REFCLK) to change due to
operating voltage and temperature, while not affecting the
design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK , exceeds the skew handling capabilities
of the Phase-align Buffer, an error is reported on the
associated TXPERx output. This output indicates a continuous
error until the Phase-align Buffer is reset. While the error
remains active, the transmitter for the associated channel will
output a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes, it is also possible to reset the
Phase-align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is
configured for generation of atomic Word Sync Sequences
(TXMODE[1] = MID) and a Phase-align Buffer error is present,
the transmission of a Word Sync Sequence will re-center the
Phase-align Buffer and clear the error condition.^[7]
Parity Support
In addition to the ten data and control bits that are captured at
each transmit Input Register, a TXOPx input is also available
on each channel. This allows the CYP(V)15G0401DXB to
support ODD parity checking for each channel. Parity
checking is available for all operating modes (including
Encoder Bypass). The specific mode of parity checking is
controlled by the PARCTL input, and operates per Table 2.
Table 2. Input Register Bits Checked for Parity ^[8]
Transmit Parity Check Mode (PARCTL)
Signal
Name
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
TXOPx
LOW
MID
TXMODE[1]
= LOW
X ^[9]
TXMODE[1]
LOW
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH
X
X
X
X
X
X
X
X
X
X
X
When PARCTL is MID (open) and the Encoders are enabled
(TXMODE[1] LOW), only the TXDx[7:0] data bits are
checked for ODD parity along with the associated TXOPx bit.
When PARCTL = HIGH with the Encoder enabled (or MID with
the Encoder bypassed), the TXDx[7:0] and TXCTx[1:0] inputs
are checked for ODD parity along with the associated TXOPx
bit. When PARCTL = LOW, parity checking is disabled.
When parity checking and the Encoder are both enabled
(TXMODE[1] LOW), the detection of a parity error causes a
C0.7 character of proper disparity to be passed to the Transmit
Shifter. When the Encoder is bypassed (TXMODE[1] = LOW,
LOW), detection of a parity error causes a positive disparity
version of a C0.7 transmission character to be passed to the
Transmit Shifter.
Notes:
6. The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.
7. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a
complete 16-character Word Sync Sequence for proper Receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word
Sync Sequence to ensure proper operation.
8. Transmit path parity errors are reported on the associated TXPERx output.
9. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.
Document #: 38-02002 Rev. *K
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