CYP15G0401DXB Datasheet, PDF (13/53 Pages) Cypress Semiconductor – Quad HOTLink II Transceiver

CYP15G0401DXB
CYV15G0401DXB
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name
I/O Characteristics
Signal Description
REFCLK
Differential LVPECL or
single-ended
LVTTL Input Clock
Reference Clock. This clock input is used as the timing reference for the transmit
PLL. It is also used as the centering frequency of the Range Controller block of the
Receive CDR PLLs.This input clock may also be selected to clock the transmit and
receive parallel interfaces. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLK input, and
leave the alternate REFCLK input open (floating). When driven by an LVPECL clock
source, the clock must be a differential clock, using both inputs. When TXCKSEL =
LOW, REFCLK is also used as the clock for the parallel transmit data (input) interface.
When RXCKSEL = LOW, the Elasticity Buffer is enabled and REFCLK is used as the
clock for the parallel receive data (output) interface.
If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from
the data stream to compensate for frequency differences between the reference clock
and recovered clock. When an addition happens, a K28.5 will be appended immedi-
ately after a framing is detected in the Elasticity Buffer. When deletion happens, a
framing character will be removed from the data stream when detected in the Elasticity
Buffer.
Analog I/O and Control
OUTA1
OUTB1
OUTC1
OUTD1
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
OUTA2
OUTB2
OUTC2
OUTD2
CML Differential
Output
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
INA1
INB1
INC1
IND1
LVPECL Differential Input Primary Differential Serial Data Inputs. These inputs accept the serial data stream
for deserialization and decoding. The INx1 serial streams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when INSELx =
HIGH.
INA2
INB2
INC2
IND2
LVPECL Differential Input Secondary Differential Serial Data Inputs. These inputs accept the serial data
stream for deserialization and decoding. The INx2 serial streams are passed to the
receiver Clock and Data Recovery (CDR) circuits to extract the data content when
INSELx = LOW.
INSELA
INSELB
INSELC
INSELD
SDASEL
LVTTL Input,
asynchronous
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1 input is selected.
When LOW, the INx2 input is selected.
Three-level Select ^[5]
Signal Detect Amplitude Level Select. Allows selection of one of three predefined
static configuration input amplitude trip points for a valid signal indication, as listed in Table 12.
LPEN
LVTTL Input,
asynchronous,
internal pull-down
All-Port Loop-Back Enable. Active HIGH. When asserted (HIGH), the transmit serial
data from each channel is internally routed to the associated receiver Clock and Data
Recovery (CAR) circuit. All enabled serial drivers are forced to differential logic “1.”
All serial data inputs are ignored.
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the
signals on the BOE[7:0] inputs directly control the OUTxy differential drivers. When
the BOE[x] input is HIGH, the associated OUTxy differential driver is enabled. When
the BOE[x] input is LOW, the associated OUTxy differential driver is powered down.
The specific mapping of BOE[7:0] signals to transmit output enables is listed in
Table 10. When OELE returns LOW, the last values present on BOE[7:0] are captured
in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW),
the latch is reset to disable all outputs.
Document #: 38-02002 Rev. *K
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