CY7C1516V18 Datasheet, PDF (16/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 2-Word Burst Architecture

TAP AC Switching Characteristics Over the Operating Range^{[12, 13]} (continued)
Parameter
Description
Set-up Times
t_TMSS
TMS Set-up to TCK Clock Rise
t_TDIS
TDI set-up to TCK Clock Rise
t_CS
Capture Set-up to TCK Rise
Hold Times
t_TMSH
TMS Hold after TCK Clock Rise
t_TDIH
TDI Hold after Clock Rise
t_CH
Capture Hold after Clock Rise
Output Times
t_TDOV
t_TDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TAP Timing and Test Conditions^[13]
0.9V
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Min.
Max.
Unit
5
ns
5
ns
5
ns
5
ns
5
ns
5
ns
10
ns
0
ns
TDO
Z₀ = 50Ω
50Ω
C_L = 20 pF
(a) GND
0V
t_TH
t_TL
ALL INPUT PULSES
1.8V
0.9V
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
t_TMSS
t_TDIS
t_TCYC
t_TMSH
t_TDIH
Test Data-Out
TDO
t_TDOV
t_TDOX
Document #: 38-05563 Rev. *D
Page 16 of 28
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