CY7C1371B Datasheet, PDF (16/26 Pages) Cypress Semiconductor – 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture

CY7C1371B
CY7C1373B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −55°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on V_DD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State^[13]....................................−0.5V to V_DDQ + 0.5V
DC Input Voltage^[13]................................−0.5V to V_DDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Ambient
Range Temperature^[12]
V_DD
Commercial 0°C to +70°C 3.3V –5% /
Industrial –40°C to +85°C ^+10%
V_DDQ
2.5V – 5%
3.3V + 10%
Electrical Characteristics Over the Operating Range^[14]
Parameter
Description
Test Conditions
V_DD
V_DDQ
V_OH
V_OL
V_IH
V_IL
I_X
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V_DD = Min., I_OH = –1.0 mA
V_DD = Min., I_OH = –4.0 mA
V_DD = Min., I_OL = 1.0 mA
V_DD = Min., I_OL = 8.0 mA
Input LOW Voltage
Input Load Current
Input Current of MODE
GND < V_I < V_DDQ
V_DDQ = 2.5V
V_DDQ = 3.3V
V_DDQ = 2.5V
V_DDQ = 3.3V
V_DDQ = 3.3 V
V_DDQ = 2.5V
V_DDQ = 3.3V
V_DDQ = 2.5V
Input Current of ZZ
Input = V_SS
I_OZ
Output Leakage Current GND < V_I < V_DDQ, Output Disabled
I_DD
V_DD Operating Supply
V_DD = Max., I_OUT = 0 mA,
8.5-ns cycle, 117 MHz
f = f_MAX = 1/t_CYC
10-ns cycle, 100 MHz
12-ns cycle, 83 MHz
I_SB1
Automatic CE
Max. V_DD, Device Deselected, 8.5-ns cycle, 117 MHz
Power-Down
V_IN > V_IH or V_IN < V_IL
10-ns cycle, 100 MHz
Current—TTL Inputs
f = f_MAX = 1/t_CYC
12-ns cycle, 83 MHz
I_SB2
Automatic CE
Max. V_DD, Device Deselected, All speed grades
Power-Down
V_IN < 0.3V or V_IN > V_DDQ – 0.3V,
Current—CMOS Inputs f = 0
I_SB3
Automatic CE
Max. V_DD, Device Deselected, or 8.5-ns cycle, 117 MHz
Power-Down
V_IN < 0.3V or V_IN > V_DDQ – 0.3V _{10-ns cycle, 100 MHz}
Current—CMOS Inputs f = f_MAX = 1/t_CYC
12-ns cycle, 83 MHz
I_SB4
Automatic CS
Max. V_DD, Device Deselected, All speeds
Power-Down
V_IN > V_IH or V_IN < V_IL, f = 0
Current—TTL Inputs
Notes:
12. T_A is the case temperature.
13. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
14. The load used for V_OH and V_OL testing is shown in figure (b) of AC Test Loads.
Min.
3.135
2.375
2.0
2.4
2
1.7
–0.3
–0.3
–30
–30
Max.
3.63
3.63
0.4
0.4
0.8
0.7
5
30
30
5
250
225
185
100
90
75
20
90
75
60
50
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Document #: 38-05198 Rev. **
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