CY7C1361C_12 Datasheet, PDF (16/34 Pages) Cypress Semiconductor – 9-Mbit (256 K × 36/512 K × 18) Flow-Through SRAM

CY7C1361C, CY7C1363C
TAP AC Switching Characteristics
Over the Operating Range
Parameter ^{[12, 13]}
Clock
t_TCYC
t_TF
t_TH
t_TL
Output Times
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
t_TDOV
t_TDOX
Set-up Times
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
t_TMSS
t_TDIS
t_CS
Hold Times
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
t_TMSH
t_TDIH
t_CH
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Parameter
Min
Max Unit
50
–
ns
–
20
MHz
20
–
ns
20
–
ns
–
10
ns
0
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
5
–
ns
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................V_SS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
3.3 V TAP AC Output Load Equivalent
Input pulse levels ............................................... V_SS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
TDO
Z_O= 50Ω
50Ω
20pF
TDO
Z_O= 50Ω
50Ω
20pF
Notes
12. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test conditions. t_R/t_F = 1 ns.
Document Number: 38-05541 Rev. *M
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