CYP15G0402DX Datasheet, PDF (15/27 Pages) Cypress Semiconductor – Quad HOTLinkII SERDES

PRELIMINARY
CYP15G0402DX
channels will save considerable power and will reduce system
heat generation. Controlling system power dissipation will
improve the system reliability.
Receive Channel Power-Control Latch Enable. Active HIGH.
When RXLE is HIGH, the signals on the BOE[7:0] inputs
directly control the power enables for the receive PLLs and
analog circuits. When the BOE[7:0] input is HIGH, the
associated receive channel [A.D] PLLs and analog logic are
active. When the BOE[7:0] input is LOW, the associated
receive channel [A.D] PLL’s and analog circuits are in a power
down mode. When RXLE returns LOW, the last values present
on BOE[7:0] are captured. The channels controlled by
BOE[7:0] signals are listed in Table 2.
When RXLE is HIGH and BOE[x] is HIGH, the associated
receive channel is enabled to receive a serial stream from the
selected line receiver. When RXLE is HIGH and BOE[x] is
LOW, the associated receive channel is disabled and powered
down.
Any disabled channel will indicate a constant /LFIx output.
When a disabled receive channel is re-enabled, the status of
the associated LFIx output and data on the parallel outputs for
the associated channel may be indeterminate for up to 10 ms.
After powering the chip, the Transmitter may assume either a
positive or negative value for its initial running disparity. Upon
transmission of any Transmission Character, the transmitter
will select the proper version of the Transmission Character
When OELE is HIGH and BOE[x] is HIGH, the associated
serial driver is enabled. When OELE is HIGH and BOE[x] is
LOW, the associated driver is disabled and powered down. If
both outputs for a channel are disabled, the internal logic for
that channel is powered down. When OELE returns LOW, the
values present on the BOE[7:0] inputs are latched in the
Output Enable Latch.
Output Bus
Each receive channel presents a 12-signal output bus
consisting of:
• a 10-bit data bus
• a COMMA detect indicator
• a parity bit.
The receive decoder assigns the bit values per Table 7.
The externally encoded data, the RXDx[0] corresponds to the
MSB of the 10 bit data. The signals present on this output bus
are shown in Table 8.
The framed 10-bit value is presented to the associated Output
Register, along with a status output indicating if the character
in the output register matches the selected framing characters.
The COMDETx status outputs operate the same regardless of
the bit combination selected for character framing by the
FRAMCHAR input. Characters in Table 5 will cause COMDET
assertion, all others characters are mapped to invalid
characters. COMDETx is HIGH when the character in the
output register of the associated channel contains the selected
framing character at the proper character boundary, and LOW
for all other bit combinations.
When the low-latency framer and half-rate receive port
clocking are enabled, RFMODE and RXRATE are both LOW,
the framer will stretch the recovered clock to the next 20-bit
boundary such that the rising edge of RXCLKx+ occurs when
COMDET is present on the associated output bus.
Document #: 38-02023 Rev. *B
Table 7. Output Register Bit Assignments ^[4]
Signal Name
RXSTx[2] (LSB)
COMDETx
RXSTx[1]
DOUTx[0]
RXSTx[0]
DOUTx[1]
RXDx[0]
DOUTx[2]
RXDx[1]
DOUTx[3]
RXDx[2]
DOUTx[4]
RXDx[3]
DOUTx[5]
RXDx[4]
DOUTx[6]
RXDx[5]
DOUTx[7]
RXDx[6]
DOUTx[8]
RXDx[7] (MSB)
DOUTx[9]
Note:
4. The RXOPx outputs are also driven from the associated output reg-
ister, but their interpretation is under the separate control of PARCTL.
Table 8. Output Register Bit Assignments
Signal Name
RXOPx^[5]
COMDET^[5]
RXDx[0] (LSB)
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
RXDx[8]
RXDx[9] (MSB)
Bus Weight
2⁰
2¹
2²
2³
2⁴
2⁵
2⁶
2⁷
2⁸
2⁹
10B Name
a^[6]
b
c
d
e
i
f
g
h
j
5. The RXOPx and COMDETx outputs are also driven from the associated
output register, but their generation and interpretation are separate from
the data bus.
6. LSB will be shifted in first.
When the standard framer is enabled and half-rate receive
port clocking are enabled, RFMODE is not low and RXRATE
is LOW, the output clock is not modified, but a single pipeline
stage may be added or subtracted from the data stream by the
framer logic such that the rising edge of RXCLKx+ occurs
when COMDET is present on the associated output bus.
This adjustment only occurs when the framer for that channel
is enabled (RFENx is HIGH). When the framer is disabled, the
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