CY7C09089 Datasheet, PDF (15/19 Pages) Cypress Semiconductor – 64K/128K x 8/9 Synchronous Dual-Port Static RAM

CY7C09089/99
CY7C09189/99
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)^{[17, 24, 30, 31]}
CLK
t_CYC2
t_CH2
t_CL2
ADDRESS
INTERNAL
A_X
ADDRESS
R/W
t_SAD
ADS
t_SCN
CNTEN
t_SRST
CNTRST
DATA_IN
DATA_OUT
0
t_SW t_HW
t_HAD
t_HCN
t_HRST
t_SD t_HD
D₀
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
t_SA t_HA
A_n
1
A_n+1
A_n
A_n+1
Q₀
Q₁
Q_n
READ
ADDRESS 1
READ
ADDRESS n
Notes:
30. CE₀ = V_IL; CE₁ = V_IH.
31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06039 Rev. *A
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