CY7C09089 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 64K/128K x 8/9 Synchronous Dual-Port Static RAM

25/0251
CY7C09089/99
CY7C09189/99
64K/128K x 8/9
Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Six Flow-Through/Pipelined devices
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5^[1]/7.5/9/12 ns
(max.)
• Low operating power
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70908
and IDT709089
Logic Block Diagram
R/W_L
OE_L
R/W_R
OE_R
CE_0L
1
CE_1L
0
0/1
1
CE_0R
0
CE_1R
0/1
FT/Pipe_L
[2]
I/O_0L–I/O_7/8L
1
0
0/1
8/9
[3]
A₀–A_15/16L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
16/17
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0
1
0/1
8/9
FT/Pipe_R
[2]
I/O_0R–I/O_7/8R
Counter/
Address
Register
Decode
16/17
[3]
A₀–A_15/16R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
Notes:
1. See page 7 for Load Conditions.
2. I/O₀–I/O₇ for x8 devices; I/O₀–I/O₈ for x9 devices.
3. A₀–A₁₅ for 64K; and A₀–A₁₆ for 128K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06039 Rev. *A
Revised December 27, 2002