W320-03 Datasheet, PDF (14/19 Pages) Cypress Semiconductor – 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

PWRGD# Timing Diagrams
PRELIMINARY
W320-03
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
VCC W320 CLOCK
GEN
CLOCK STATE
CLOCK VCO
CLOCK OUTPUTS
Possible glitch while Clock VCC is coming
up. Will be gone in 0.2–0.3 ms delay.
State 0
OFF
0.2 – 0.3 ms Wait for _Sample
delay _{PWRGD# BSELS}
State 1 State 2 State 3
ON
OFF
ON
Figure 2. CPU Power BEFORE Clock Power.
GND VRM 5/12V
PWRGD#
VID [3:0]
BSEL [1:0]
PWRGD# FROM
VRM
PWRGD# FROM
NPN
VCC CPU CORE
PWRGD#
VCC W320 CLOCK
GEN
State 0
CLOCK STATE
OFF
CLOCK VCO
OFF
LOCK OUTPUTS
0.2 – 0.3 ms
delay
State 1
Wait for
PWRGD#
Sample
BSELS
State 2
State 3
ON
ON
Figure 3. CPU Power AFTER Clock Power.
Document #: 38-07248 Rev. **
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