PSOC4XXX8-BLE Datasheet, PDF (14/47 Pages) Cypress Semiconductor – Programmable System-on-Chip

PRELIMINARY
PSoC^® 4: PSoC 4XX8_BLE
Family Datasheet
Table 2. PSoC 4XX8_BLE Pin List (WLCSP Package) (continued)
Pin
Name
Type
Description
G6
VSSR
GROUND Radio ground
G7
VSSR
GROUND Radio ground
G8
GANT
GROUND Antenna shielding ground
G9
VSSR
GROUND Radio ground
H1
NC
NC
Do not connect
H2
P0.5
GPIO
Port 0 Pin 5, analog/digital/lcd/csd
H3
P0.1
GPIO
Port 0 Pin 1, analog/digital/lcd/csd
H4
XTAL24O
CLOCK
24-MHz crystal
H5
XTAL24I
CLOCK
24-MHz crystal or external clock input
H6
VSSR
GROUND Radio ground
H7
VSSR
GROUND Radio ground
H8
ANT
ANTENNA Antenna pin
J1
NC
NC
Do not connect
J2
P0.4
GPIO
Port 0 Pin 4, analog/digital/lcd/csd
J3
P0.0
GPIO
Port 0 Pin 0, analog/digital/lcd/csd
J4
VDDR
POWER 1.9-V to 5.5-V radio supply
J7
VDDR
POWER 1.9-V to 5.5-V radio supply
J8
NO CONNECT
–
–
High-speed I/O matrix (HSIOM) is a group of high-speed
switches that routes GPIOs to the resources inside the device.
These resources include CapSense, TCPWMs, I²C, SPI, UART,
and LCD. HSIOM_PORT_SELx are 32-bit-wide registers that
control the routing of GPIOs. Each register controls one port; four
dedicated bits are assigned to each GPIO in the port. This
provides up to 16 different options for GPIO routing as shown in
Table 3.
Table 3. HSIOM Port Settings
Table 3. HSIOM Port Settings (continued)
Value
Description
11
Reserved
12
Pin is an LCD common pin
13
Pin is an LCD segment pin
14
Pin-specific Deep-Sleep function #0
15
Pin-specific Deep-Sleep function #1
Value
Description
0
Firmware-controlled GPIO
1
Output is firmware-controlled, but Output Enable (OE)
is controlled from DSI.
2
Both output and OE are controlled from DSI.
3
Output is controlled from DSI, but OE is
firmware-controlled.
4
Pin is a CSD sense pin
5
Pin is a CSD shield pin
6
Pin is connected to AMUXA
7
Pin is connected to AMUXB
8
Pin-specific Active function #0
9
Pin-specific Active function #1
10
Pin-specific Active function #2
Document Number: 001-94624 Rev. *K
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