|
PSOC4XXX8-BLE Datasheet, PDF (1/47 Pages) Cypress Semiconductor – Programmable System-on-Chip | |||
|
PRELIMINARY
PSoC® 4: PSoC 4XX8_BLE
Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortexâ¢-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4XX8_BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy
(BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic,
high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4XX8_BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications
and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
â 48-MHz ARM Cortex-M0 CPU with single-cycle multiply
â Up to 256 KB of flash with Read Accelerator
â Up to 32 KB of SRAM
BLE Radio and Subsystem
â 2.4-GHz RF transceiver with 50-⦠antenna drive
â Digital PHY
â Link-Layer engine supporting master and slave modes
â RF output power: â18 dBm to +3 dBm
â RX sensitivity: â92 dBm
â RX current: 18.7 mA
â TX current: 16.5 mA at 0 dBm
â RSSI: 1-dB resolution
Programmable Analog
â Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability. Can operate in Deep Sleep mode.
â 12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
â Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
â Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
â Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and data path
â Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Power Management
â Active mode: 1.7 mA at 3-MHz flash program execution
â Deep Sleep mode: 1.3 µA with watch crystal oscillator (WCO)
on
â Hibernate mode: 150 nA with RAM retention
â Stop mode: 60 nA
Capacitive Sensing
â Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and liquid tolerance
â Cypress-supplied software component makes capacitive
sensing design easy
â Automatic hardware tuning algorithm (SmartSenseâ¢)
Segment LCD Drive
â LCD drive supported on all pins (common or segment)
â Operates in Deep Sleep mode with four bits per pin memory
Serial Communication
â Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
â Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
â Center-aligned, Edge, and Pseudo-random modes
â Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIOs
â 7 mm à 7 mm 56-pin QFN package
â 76-ball CSP and thin CSP packages
â Any GPIO pin can be CapSense, LCD, analog, or digital
â Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
PSoC Creator⢠Design Environment
â Integrated Design Environment (IDE) provides schematic
design entry and build (with analog and digital automatic
routing)
â API components for all fixed-function and programmable
peripherals
Industry-Standard Tool Compatibility
â After schematic entry, development can be done with
ARM-based industry-standard development tools
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 001-94624 Rev. *K
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised May 11, 2016
|
▷ |