MB3793-34A Datasheet, PDF (14/26 Pages) Cypress Semiconductor – Precise detection of power voltage fall: 2.5%

MB3793-34A
9. Operation Sequence
9.1 Positive clock pulse input
Refer to “8.1. Basic operation (positive clock pulse)” under “8. Timing Diagram”.
9.2 Negative clock pulse input
Refer to “8.2. Basic operation (negative clock pulse)” under “8.Timing Diagram”.
The MB3793 operates in the same way whether it inputs positive or negative pulses.
9.3 Single-clock input monitoring
To use the MB3793 while monitoring only one clock, connect clock pins CK1 and CK2.
Although the MB3793 operates basically in the same way as when monitoring two clocks, it monitors the clock signal at every other
input pulse.
Refer to “8.3. Single-clock input monitoring (positive clock pulse)” under “8.Timing Diagram”.
9.4 Description of Operations
The numbers given to the following items correspond to numbers 1 to 13 used in “8.Timing Diagram”.
1. The MB3793 outputs a reset signal when the supply voltage (V_CC) reaches about 0.8 V (V_CCL).
2. If V_CC reaches or exceeds the rise-time detected voltage V_SH, the MB3793 starts charging the power-on reset hold time setting
capacitor C_TP. At this time, the output remains in a reset state. The V_SH value is 3.48 V (Typ).
3. When C_TP has been charged for a certain period of time T_PR (until the CTP pin voltage exceeds the threshold voltage (V_th) after
the start of charging), the MB3793 cancels the reset (setting the RESET pin to “H” level from “L” level).
The V_th value is about 3.6 V with V_CC = 5.0 V
Tt_Ph_Re(mposw) e_.=.r-Aon_rCes_Te_Pt(h_oFl)d time t_PR is set with the following equation:
The value of A is about 1300 with V_CC = 5.0 V. The MB3793 also starts charging the watchdog timer monitor time setting capacitor
(C_TW).
4. When the voltage at the watchdog timer monitor time setting pin C_TW reaches the “H” level threshold voltage V_H, the CTW switches
from the charge state to the discharge state.
The value of V_H is always about 1.24 V regardless of the detected voltage.
5. If the CK2 pin inputs a clock pulse (positive edge trigger) when the C_TW is being discharged in the CK1-CK2 order or simultaneously,
the C_TW switches from the discharge state to the charge state.
The MB3793 repeats operations 4 and 5 as long as the CK1/CK2 pin inputs clock pulses with the system logic circuit operating
normally.
6. If no clock pulse is fed to the CK1 or CK2 pin within the watchdog timer monitor time t_WD due to some problem with the system
logic circuit, the CTW pin is set to the “L” level threshold voltage V_L or less and the MB3793 outputs a reset signal (setting the
RESET pin to “L” level from “H” level).
The value of V_L is always about 0.24 V regardless of the detected voltage.
The
t_WD
(wmastc) ^h.=.dBog^tiCm_T^e_W^r
m(_oFn)it_orCtim× eCt_TWPD(μisF)set
with
the
following
equation:
The value of B is hardly affected by the power supply voltage; it is about 1500 with V_CC = 5.0 V.
The value of C is 0.
For
t_WD
t(hmiss)re_.=a_. sBo×n:C_TW
(μF)
Document Number: 002-08556 Rev. *A
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