CY7C64601 Datasheet, PDF (14/42 Pages) Cypress Semiconductor – EZ-USB FX USB Microcontroller Data Sheet

CY7C64601/603/613
3.2 CY7C646xx Pin Descriptions (continued)
128 80 52
Name
Type Default
Description
30 16 11 PA5 or
FRD# or
RDY5 or
SLRD
I/O/Z
I
(PA5)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FRD# is the write strobe output for an external FIFO connected to
the data bus D[7..0]. If the FRD# pin is used, it should be externally
pulled up to V_CC to ensure that the read strobe is inactive at power-
on.
RDY5 is a GPIF input signal.
SLRD is the read strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
31 17
PA6 or
RXD0OUT
I/O/Z
I
(PA6)
Multiplexed pin whose function is selected by the PORTACFG.6 bit.
PA6 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
32 18
PA7 or
RXD1OUT
I/O/Z
I
(PA7)
Multiplexed pin whose function is selected by the PORTACFG.7 bit.
PA7 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In modes
1, 2, and 3, this pin is HIGH.
Port B
The following descriptions apply to the PORT B pins:
79 47 29 PB0 or
T2 or
D[0] or
GDA[0] or
AFI [0]
80 48 30 PB1 or
T2EX or
D[1] or
GDA[1] or
AFI [1]
81 49 31 PB2 or
RXD1 or
D[2] or
GDA[2] or
AFI [2]
I/O/Z
I/O/Z
I/O/Z
I
(PB0)
I
(PB1)
I
(PB2)
D[7..0] is the 8051 data bus. This bus is optionally available on
PORT B pins to provide access to the 8051 data bus in smaller EZ-
USB II packages that do not bring out the 8051 address and data
buses.
GDA[7..0] is the GPIF A data bus.
AFI[7..0] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.0 and IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which pro-
vides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does
not use this pin.
AFI [0] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.1 and IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX re-
loads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
AFI [1] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.2 and IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
RXD1is an active-HIGH input signal for 8051 UART1, which pro-
vides data to the UART in all modes.
AFI [2] is the bidirectional A-FIFO data bus.
Document #: 38-08005 Rev. **
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