CY7C1441AV33 Datasheet, PDF (14/31 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
TAP Timing
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
1
2
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
tTL
tTMSS tTMSH
tCYC
tTDIS tTDIH
Test Data-In
(TDI)
tTDOV
Test Data-Out
(TDO)
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range^{[9, 10]}
Parameter
Description
Clock
t_TCYC
TCK Clock Cycle Time
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH time
t_TL
TCK Clock LOW time
Output Times
t_TDOV
TCK Clock LOW to TDO Valid
t_TDOX
TCK Clock LOW to TDO Invalid
Set-up Times
t_TMSS
TMS Set-up to TCK Clock Rise
t_TDIS
TDI Set-up to TCK Clock Rise
t_CS
Capture Set-up to TCK Rise
Hold Times
t_TMSH
t_TDIH
t_CH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Min.
50
20
20
0
5
5
5
5
5
5
Max.
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
9. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. t_R/t_F = 1 ns.
Document #: 38-05357 Rev. *F
Page 14 of 31
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