CY7C1371D_07 Datasheet, PDF (14/29 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture

TAP AC Switching Characteristics Over the Operating Range^{[10, 11]}
Parameter
Description
Clock
t_TCYC
TCK Clock Cycle Time
t_TF
TCK Clock Frequency
t_TH
TCK Clock HIGH time
t_TL
TCK Clock LOW time
Output Times
t_TDOV
t_TDOX
Setup Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
t_TMSS
t_TDIS
t_CS
Hold Times
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
t_TMSH
t_TDIH
t_CH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
CY7C1371D
CY7C1373D
Min
Max
Unit
50
ns
20
MHz
20
ns
20
ns
10
ns
0
ns
5
ns
5
ns
5
ns
5
ns
5
ns
5
ns
Notes:
10. t_CS and t_CH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t_R/t_F = 1 ns.
Document #: 38-05556 Rev. *F
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