CY14B104L_09 Datasheet, PDF (14/25 Pages) Cypress Semiconductor – 4 Mbit (512K x 8/256K x 16) nvSRAM

CY14B104L, CY14B104N
Hardware STORE Cycle
Parameters
Description
t_PHSB
t_HLBL
Hardware STORE Pulse Width
Hardware STORE LOW to STORE Busy
Switching Waveforms
Figure 14. Hardware STORE Cycle^[21]
:ULWHODWFKVHW
+6%,1
W_3+6%
+6%287
'4'DWD2XW
W_+/%/
W_'(/$<
W₆₇₂₅₍
CY14B104L/CY14B104N
Unit
Min
Max
15
ns
500
ns
W_+++'
W_/=+6%
:ULWHODWFKQRWVHW
W_3+6%
+6%,1
W_+/%/
+6%287
W_'(/$<
'4'DWD2XW
W_+++'
W_/=+6%
$GGUHVV
&(
9_&&
Figure 15. Soft Sequence Processing^{[27, 28]}
6RIW6HTXHQFH
W₆₆
&RPPDQG
$GGUHVV
W_6$
$GGUHVV
W_&:
6RIW6HTXHQFH
W₆₆
&RPPDQG
$GGUHVV
$GGUHVV
W_&:
Notes
27. This is the amount of time it takes to take action on a soft sequence command. V_CC power must remain HIGH to effectively register command.
28. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07102 Rev. *L
Page 14 of 25
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