CY7S1049G Datasheet, PDF (13/21 Pages) Cypress Semiconductor – 4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)

CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 10. Read Cycle No. 3 (OE Controlled) ^{[27, 28, 29]}
ADDRESS
CE
OE
t_RC
t_ACE
t_DOE
t_LZOE
tPD
t _HZCE
t _HZOE
DATA I /O
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
t_LZCE
t_PU
DATA OUT VALID
HIGH
IMPEDANCE
I_SB
Notes
27. WE is HIGH for read cycle.
28. Address valid prior to or coincident with CE LOW transition.
29. DS must be HIGH for chip access
Document Number: 001-95414 Rev. *C
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