CY7S1049G Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)

CY7S1049G
CY7S1049GE
4-Mbit (512K words × 8 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■ High speed
❐ Access time (t_AA) = 10 ns / 15 ns
■ Ultra-low power Deep-Sleep (DS) current
❐ I_DS = 15 µA
■ Low active and standby currents
❐ Active Current I_CC = 38-mA typical
❐ Standby Current I_SB2 = 6-mA typical
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
■ Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)
molded SOJ
Functional Description
The CY7S1049G/CY7S1049GE is a high-performance
PowerSnooze™ static RAM organized as 512K words × 8 bits.
This device features fast access times (10 ns) and a unique
ultra-low power Deep-Sleep mode. With Deep-Sleep mode
currents as low as 15 µA, the CY7S1049G/CY7S1049GE
devices combine the best features of fast and low- power SRAMs
in industry-standard package options. The device also features
embedded ECC. logic which can detect and correct single-bit
errors in the accessed location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O₀ through I/O₇) and address pins (A₀
through A₁₈) respectively.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O₀
through I/O₇).
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1049G is available in 44-pin TSOP II, and 36-pin
Molded SOJ (400 Mils).
Product Portfolio
Product ^[1]
Range
CY7S1049G(E)18
CY7S1049G(E)30
CY7S1049G(E)
Industrial
V_CC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
Speed
(ns)
15
10
10
Power Dissipation
Operating
(mA)
I_CC,
f = f_max
Typ ^[2] Max
Standby,
(mA)
I_SB2
Typ ^[2] Max
Deep-Sleep
current (µA)
Typ ^[2] Max
–
40
6
8
–
15
38
45
38
45
Notes
1. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
2.
Typical values are included for reference only and are not guaranteed
(for V_CC range of 2.2 V–3.6 V), and V_CC = 5 V (for V_CC range of 4.5
or tested.
V–5.5 V),
Typical values
T_A = 25 °C.
are
measured
at
V_CC
=
1.8
V
(for
V_CC
range
of
1.65
V–2.2
V),
V_CC
=
3
V
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95414 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2016