CY62162G Datasheet, PDF (13/20 Pages) Cypress Semiconductor – 16-Mbit (512 K × 32) Static RAM with Error-Correcting Code (ECC)

CY62162G/CY62162GE MoBL^®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled) ^{[28, 29, 30, 31]}
ADDRESS
CE
WE
tWC
t_SA
tSCE
t_AW
t_HA
t_PWE
t_BW
B_A-D
OE
DATA I/O
t_HZOE
NOTE 32
tSD
t_HD
DATA_IN VALID
Notes
28. The internal write time of the memory is defined by the overlap of CE and WE LOW. Chip enable must be active and WE and byte enables must be LOW to initiate a
write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
29. Data I/O is high impedance if OE or B_A, B_B, B_C, B_D = V_IH.
30. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
31. CE refers to a combination of CE₁ and CE₂. CE is LOW when CE₁ is LOW and CE₂ is HIGH. CE is HIGH when CE₁ is HIGH or CE₂ is LOW.
32. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-81598 Rev. *C
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