CY62162G Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 16-Mbit (512 K × 32) Static RAM with Error-Correcting Code (ECC)

CY62162G/CY62162GE MoBL^®
16-Mbit (512 K × 32) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (512 K × 32) Static RAM with Error-Correcting Code (ECC)
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 μA
❐ Maximum standby current: 16 μA
■ High speed: 45 ns / 55 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Easy memory expansion with CE₁ and CE₂ features
■ Available in Pb-free 119-ball PBGA package, 512 K × 32 bits
SRAM
Functional Description
The CY62162G and CY62162GE devices are high performance
CMOS MoBL SRAM organized as 512K words by 32-bits. Both
CY62162G and CY62162GE are available with dual chip
enables. CY62162GE includes an error indication pin that
signals the host processor in the case of a single bit
error-detection and correction event. It is ideal for providing More
Battery Life™ (MoBL^®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that reduces power consumption when addresses are
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE₁
HIGH or CE₂ LOW or B_A-D HIGH). The input and output pins
(I/O₀ through I/O₃₁) are placed in a high impedance state when
deselected (CE₁ HIGH or CE₂ LOW) or outputs are disabled (OE
HIGH) or the byte selects are disabled (B_A-D HIGH).
To write to the device, take chip enables (CE₁ LOW, CE₂ HIGH)
and write enable (WE) input LOW. If byte enable A (B_A) is LOW,
then data from I/O pins (I/O₀ through I/O₇) is written into the
location specified on the address pins (A₀ through A₁₈). If byte
enable B (B_B) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₈). Likewise, B_C and B_D correspond with the I/O
pins I/O₁₆ to I/O₂₃ and I/O₂₄ to I/O₃₁, respectively.
To read from the device, take chip enables (CE₁ LOW, CE₂
HIGH), and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If the first byte enable (B_A) is LOW, then data
from the memory location specified by the address pins appear
on I/O₀ to I/O₇. If byte enable (B_B) is LOW, then data from
memory appears on I/O₈ to I/O₁₅. Likewise, B_C and B_D
correspond to the third and fourth bytes. During Read operation,
in case of a single bit error detection and correction, ERR is
asserted HIGH^[1]. See the Truth Table – CY62162G /
CY62162GE on page 15 for a complete description of read and
write modes.
CY62162G and CY62162GE devices are available in a 119-ball
PBGA package with center power and ground pinout.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-81598 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2015