CY29430 Datasheet, PDF (13/24 Pages) Cypress Semiconductor – Low-noise PLL for high-performance clock applications

CY29430
LF Low Frequency Reference
(TCXO reference input)
Parameter^[15]
Description
f_IN
t_DC
V_PP
V_IL
V_IH[16]
t_R
t_F
PN_10K
PN_100K
PN_1M
Input frequency
Input duty cycle
pk-pk input swing
Input low voltage
Input high voltage
Input rise time
Input fall time
Input phase noise
Input phase noise
Input phase noise
Test Conditions
–
Measured at 1/2 input swing
AC coupled input
DC coupled input
DC coupled input
20%–80% of input
20%–80% of input
10 kHz offset
100 kHz offset
1 MHz offset
Min
Typ
Max Units
50
–
60
MHz
40
–
60
%
0.8
–
1.2
V
–
–
0.2
V
0.8
–
1.2
V
–
–
1.5
ns
–
–
1.5
ns
–
–
–151 dBc/Hz
–
–
–155 dBc/Hz
–
–
–156 dBc/Hz
Timing Parameters
Parameter^[15]
Description
Min
t_PU
t_WAKEUP[16]
Supply ramp time (0.5 V to V_DD(min)).
Time from minimum specified power supply to <+ 0.1 ppm accurate output
frequency clock, programmable (Clock stable within 2.2 ms (max) from VDDX Level,
refer to Input Clock Measurement Point)
0.01
–
Time from minimum specified power supply to <+ 0.1 ppm accurate output
–
frequency clock, programmable (Clock stable within 5.8 ms (max) from VDDX Level,
refer to Input Clock Measurement Point)
t_OEEN
Time from OE edge to output enable
–
t_OEDIS
Time for OE edge to output disable
–
t_FS
Time form FS change to new frequency
–
t_FSAMLL
Frequency change time for small trigger ( ±500ppm)
–
t_FLARGE
Frequency change time for large trigger (> ±500ppm)
–
t_CLOCK
Clock stable time delay from VDD ramp (see Figure 5), normal configuration
–
Clock stable time delay from VDD ramp (see Figure 5), delay programmed
–
Max Unit
3000 ms
10
ms
15
2.5
ms
10
s
2.5
ms
400
s
2.5
ms
2.2
ms
5.8
Input Clock Measurement Point
Parameter
Description
V_DDX[15, ^17]
t_CLOCK Measurement Point
Test Conditions
Min
Typ
Max Unit
Supply voltage 1.8 V
1.4
–
–
V
Supply voltage 2.5 V
1.8
–
–
Supply voltage 3.3 V
2.3
–
–
Notes
15. Parameters are guaranteed by design and characterization. Not 100% tested in production.
16. V_IH should not to exceed 0.5V when VDD = 0V.
17. Applies to TCXO/External Clock Input.
Document Number: 002-11000 Rev. *E
Page 13 of 24