CY29430 Datasheet, PDF (1/24 Pages) Cypress Semiconductor – Low-noise PLL for high-performance clock applications

CY29430
High-Performance Clock Synthesizer
High-Performance Clock Synthesizer
Features
■ Low-noise PLL for high-performance clock applications
■ Differential Clock Output: Four frequencies selectable,
reconfigurable by I²C
■ Output frequency support from 15 MHz to 2.1 GHz
■ Fractional N PLL with fully integrated VCO
■ Works on third overtone (OT3) of a fixed frequency crystal, Low
frequency fundamental (LFF), High frequency fundamental
(HFF) mode crystal and Low Frequency Input
■ LVPECL, CML, HCSL, LVDS or LVCMOS output standards
available
■ Compatible with 3.3 V, 2.5 V, and 1.8 V supply
■ 150 fs typical integrated jitter performance (12 kHz to 20 MHz
frequency offsets) for output greater than 150 MHz
■ VCXO functionality provided with tunable Total Pull Range
(TPR) from +/- 50 ppm to +/- 275 ppm
■ 16 pin QFN package: 3 × 3 × 0.6 mm
Functional Description
The CY29430 is a Programmable PLL based crystal oscillator
solution with flexible output frequency options. It is field and
factory programmable for any output frequency between 15 MHz
and 2.1 GHz. Four frequencies are independently programmable
on the differential output with the frequency select (FS) pins.
Additionally, other frequency options can be configured with the
I²C interface. Using advanced design technology, it provides
excellent jitter performance across the entire output frequency
range working reliably at supply voltages from 1.8 V to 3.3 V for
ambient temperatures from –40 °C to +105 °C. This makes it
ideally suited for communications applications (for example,
OTN, SONET/SDH, xDSL, GbE, Networking, Wireless
Infrastructure), test and instrumentation applications, and high
speed data converters. Additionally, the VCXO function enables
the use of CY29430 in applications requiring a clock source with
voltage control and in discrete clocking solutions for
synchronous timing applications.
The CY29430 device configuration can be created using
ClockWizard 2.1. For programming support, contact Cypress
technical support or send an email to [e-mail].
For a complete list of related documentation, click here.
Logic Block Diagram
XOUT
XIN
Crystal
Oscillator
V_DD
GND
Fractional - N
LC VCO Based PLL
Output
Dividers
V_DDO
CLK_P
Output _{CLK_N}
Drivers
CLK_SE
Digital Configuration and Control
NVM
FS[1:0]
I2C
Interface
SCL SDA
ADC + Digital Filtering Pathway
(for VCXO Function)
VC
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-11000 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 3, 2017