CY14E101LA Datasheet, PDF (13/19 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) nvSRAM

CY14E101LA
Software Controlled STORE/RECALL Cycle
Parameters^{[21, 22]}
Description
t_RC
t_SA
t_CW
t_HA
t_RECALL
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Switching Waveforms
25 ns
Min
Max
25
0
20
0
200
45 ns
Unit
Min
Max
45
ns
0
ns
30
ns
0
ns
200
µs
Figure 9. CE and OE Controlled Software STORE/RECALL Cycle^[22]
t_RC
t_RC
Address
Address #1
t_SA
t_CW
Address #6
t_CW
CE
t_SA
OE
t_HA
t_HA
t_HA
t_HA
HSB (STORE only)
DQ (DATA)
t_LZCE
t_HZCE
t _DELAY
23
Note
High Impedance
t_STORE/t_RECALL
t_HHHD
t_LZHSB
RWI
Figure 10. Autostore Enable/Disable Cycle
Address
CE
t_SA
t_RC
Address #1
t_SA
t_CW
OE
DQ (DATA)
t_LZCE
t_HA
t_HA
t_HZCE
t_RC
Address #6
t_CW
t_HA
t_HA
23
Note
t_SS
t _DELAY
Notes
21. The software sequence is clocked with CE controlled or OE controlled reads.
22. The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE must be HIGH during all six consecutive cycles.
23. DQ output data at the sixth read may be invalid since the output is disabled at t_DELAY time.
Document #: 001-42916 Rev. *B
Page 13 of 19
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