CY14E101LA Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) nvSRAM

CY14E101LA
1 Mbit (128K x 8) nvSRAM
Features
■ 25 ns and 45 ns Access Times
■ Internally Organized as 128K x 8 (CY14E101LA)
■ Hands off Automatic STORE on Power Down with only a Small
Capacitor
■ STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
■ RECALL to SRAM Initiated by Software or Power Up
■ Infinite Read, Write, and Recall Cycles
■ 1 Million STORE Cycles to QuantumTrap
■ 20 year Data Retention
■ Single 5V +10% Operation
■ Industrial Temperature
■ 44-Pin TSOP-II Package
■ Pb-free and RoHS Compliance
Functional Description
The Cypress CY14E101LA is a fast static RAM, with a nonvol-
atile element in each memory cell. The memory is organized as
128K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
Logic Block Diagram
A₅
A₆
A₇
A₈
A₉
A ₁₂
A ₁₃
A ₁₄
A ₁₅
A ₁₆
DQ ₀
DQ ₁
DQ ₂
DQ ₃
DQ ₄
DQ ₅
DQ ₆
DQ ₇
Quantum Trap
1024 X 1024
STORE
STATIC RAM
ARRAY
1024 X 1024
RECALL
COLUMN I/O
COLUMN DEC
A₀ A₁ A₂ A₃ A₄ A₁₀ A₁₁
V_CC
V_CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
- A₁₄ A₂
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-42916 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 08, 2009
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