CY14B256LA Datasheet, PDF (13/21 Pages) Cypress Semiconductor – 256 Kbit (32K x 8) nvSRAM

CY14B256LA
AutoStore/Power Up RECALL
Parameters
Description
t_HRECALL ^[17]
t_STORE ^[18]
t_DELAY ^[19]
V_SWITCH
t_VCCRISE[10]
V_HDIS[10]
t_LZHSB[10]
t_HHHD[10]
Power Up RECALL Duration
STORE Cycle Duration
Time Allowed to Complete SRAM Write Cycle
Low Voltage Trigger Level
VCC Rise Time
HSB Output Disable Voltage
HSB To Output Active Time
HSB High Active Time
Switching Waveforms
Figure 9. AutoStore or Power Up RECALL^[20]
V_CC
V_SWITCH
V_HDIS
CY14B256LA
Min
Max
20
8
25
2.65
150
1.9
5
500
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
V_VCCRISE
t_HHHD
Note ¹⁸
t_STORE
t_LZHSB
t_HRECALL
t_DELAY
t_HHHD
Note¹⁸
t_STORE
21
Note
t_DELAY
t_LZHSB
t_HRECALL
POWER-UP
RECALL
Read & Write
BROWN POWER-UP
OUT
RECALL
AutoStore
Read & Write
POWER
DOWN
AutoStore
Unit
ms
ms
ns
V
µs
V
µs
ns
Notes
17. t_HRECALL starts from the time V_CC rises above V_SWITCH.
18. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
19. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t_DELAY.
20. Read and Write cycles are ignored during STORE, RECALL, and while V_CC is below V_SWITCH.
21. HSB pin is driven high to V_CC only by internal 100 kΩ resistor, HSB driver is disabled.
Document Number: 001-54707 Rev. *B
Page 13
[+] Feedback