CY14B104LA_12 Datasheet, PDF (13/26 Pages) Cypress Semiconductor – 4-Mbit (512 K × 8/256 K × 16) nvSRAM

CY14B104LA, CY14B104NA
Switching Waveforms (continued)
Figure 9. SRAM Write Cycle #2 (CE Controlled) ^{[32, 33, 34, 35]}
t_WC
Address
Address Valid
t_SA
t_SCE
t_HA
CE
BHE, BLE
WE
t_BW
t_PWE
t_SD
t_HD
Data Input
Data Output
Input Data Valid
High Impedance
Address
CE
BHE, BLE
WE
Data Input
Data Output
Figure 10. SRAM Write Cycle #3 (BHE and BLE Controlled) ^{[32, 33, 34, 35]}
t_WC
Address Valid
t_SCE
t_SA
t_BW
t_HA
t_AW
t_PWE
t_SD
t_HD
Input Data Valid
High Impedance
Notes
32. BHE and BLE are applicable for × 16 configuration only.
33. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
34. HSB must remain HIGH during read and write cycles.
35. CE or WE must be >V_IH during address transitions.
Document Number: 001-49918 Rev. *L
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