CYWUSB6935_10 Datasheet, PDF (12/36 Pages) Cypress Semiconductor – WirelessUSB™ LR 2.4 GHz DSSS Radio SoC

CYWUSB6935
Table 9. Receive SERDES Interrupt Enable
Addr: 0x07
7
6
Underflow B Overflow B
5
EOF B
REG_RX_INT_EN
4
3
Full B
Underflow A
2
Overflow A
Default: 0x00
1
0
EOF A
Full A
Bit Name
7 Underflow B
6 Overflow B
5 EOF B
4 Full B
3 Underflow A
2 Overflow A
1 EOF A
0 Full A
Description
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when
it is empty.
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data B register (Reg 0x0B)
s 1 = Overflow B interrupt enabled for Receive SERDES Data B
n 0 = Overflow B interrupt disabled for Receive SERDES Data B
ig ^{An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg}
s ^{0x0B) before the prior data is read out.}
e _{The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.}
D ^{1 = EOF B interrupt enabled for Channel B Receiver}
0 = EOF B interrupt disabled for Channel B Receiver
w The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
e has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field.
N ^{If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is}
cleared by reading the receive status register
for ^{The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B)}
having data placed in it.
d 1 = Full B interrupt enabled for Receive SERDES Data B
e 0 = Full B interrupt disabled for Receive SERDES Data B
d A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
n B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
e or not a complete byte has been received.
m ^{The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive}
SERDES Data A register (Reg 0x09)
m _{1 = Underflow A interrupt enabled for Receive SERDES Data A}
o _{0 = Underflow A interrupt disabled for Receive SERDES Data A}
c _{An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when}
e _{it is empty.}
R _{The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive}
t _{SERDES Data A register (0x09)}
o _{1 = Overflow A interrupt enabled for Receive SERDES Data A}
N _{0 = Overflow A interrupt disabled for Receive SERDES Data A}
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg
0x09) before the prior data is read out.
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel
A Receiver.
1 = EOF A interrupt enabled for Channel A Receiver
0 = EOF A interrupt disabled for Channel A Receiver
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field.
If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared
by reading the receive status register.
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having
data written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data
A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
Document Number : 38-16008 Rev. *G
Page 12 of 36
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