CYP15G0403DXB_11 Datasheet, PDF (12/48 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver Single 3.3V supply

CYP15G0403DXB
Pin Descriptions (continued)
CYP15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to “JTAG Support” on page 26 for the methods to reset
the JTAG state machine. See Table 9 on page 22 for the initialize values of the
device configuration latches.
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level
Detector, Range Controller, and Transition Density Detector are all enabled to
determine if the RXPLL tracks REFCLKx± or the selected input serial data stream.
If the Signal Level Detector, Range Controller, or Transition Density Detector are out
of their respective limits while LDTDEN is HIGH, the RXPLL locks to REFCLK± until
such a time they become valid. The (SDASEL[A..D][1:0]) are used to configure the
trip level of the Signal Level Detector. The Transition Density Detector limit is one
transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range
Controller is used to determine if the RXPLL tracks REFCLKx± or the selected input
serial data stream. For the cases when RXCKSELx = 0 (recovered clock), it is
recommended to set LDTDEN = HIGH.
ULCA
ULCB
ULCC
ULCD
SPDSELA
SPDSELB
SPDSELC
SPDSELD
LVTTL Input,
internal pull-up
3-Level Select^[3]
static control input
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from REFCLKx±.
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s transmit and receive PLL.
LOW = 195 – 400 MBaud
MID = 400 – 800 MBaud
HIGH = 800 – 1500 MBaud
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
Receive Input Selector. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential
Serial Data Input, INx2±, is selected for the associated receive channel.
LPENA
LPENB
LPENC
LPEND
LVTTL Input,
asynchronous,
internal pull-down
Loop-Back-Enable. The LPENx input enables the internal serial loop-back for the
associated channel. When LPENx is HIGH, the transmit serial data from the
associated channel is internally routed to the associated receive Clock and Data
Recovery (CDR) circuit. All enabled serial drivers on the channel are forced to differ-
ential logic-1, and the serial data inputs are ignored. When LPENx is LOW, the
internal serial loop-back function is disabled.
Note
3. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V_SS (ground). The HIGH level is usually implemented by direct connection to V_CC (power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
Document #: 38-02065 Rev. *I
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