CYP15G0403DXB_11 Datasheet, PDF (1/48 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver Single 3.3V supply

CYP15G0403DXB
Independent Clock Quad HOTLink II™
Transceiver
Features
■ Second-generation HOTLink^® technology
■ Compliant to multiple standards
❐ ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet
(IEEE802.3z)
❐ CPRI™ compliant
❐ 8B/10B coded data or 10 bit uncoded data
■ Quad channel transceiver operates from 195 to 1500 MBaud
serial data rate
❐ Aggregate throughput of up to 12 Gbits/second
■ Second-generation HOTLink technology
■ Truly independent channels
❐ Each channel can operate at a different signaling rate
❐ Each channel can transport a different type of data
■ Selectable input/output clocking options
■ Internal phase-locked loops (PLLs) with no external PLL
components
■ Dual differential PECL-compatible serial inputs per channel
■ Internal DC-restoration
■ Dual differential PECL-compatible serial outputs per channel
❐ Source matched for 50 transmission lines
❐ No external bias resistors required
❐ Signaling-rate controlled edge-rates
■ MultiFrame™ Receive Framer provides alignment options
❐ Bit and byte alignment
❐ Comma or Full K28.5 detect
❐ Single or Multi-byte Framer for byte alignment
❐ Low-latency option
■ Synchronous LVTTL parallel interface
■ JTAG boundary scan
■ Built-In Self-Test (BIST) for at-speed link testing
■ Compatible with
❐ Fiber-optic modules
❐ Copper cables
❐ Circuit board traces
■ Per-channel Link Quality Indicator
❐ Analog signal detect
❐ Digital signal detect
■ Low-power 3W at 3.3V typical
■ Single 3.3V supply
■ 256-ball thermally enhanced BGA
■ Pb-Free package option available
■ 0.25 BiCMOS technology
Functional Description
The CYP15G0403DXB Independent Clock Quad
HOTLink II™ Transceiver is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links like optical fiber,
balanced, and unbalanced copper transmission lines. The
signaling rate can be anywhere in the range of 195 to 1500
MBaud per serial link. Each channel operates independently
with its own reference clock allowing different rates. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and then
converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into
characters, and presents these characters to an Output
Register. Figure 1 on page 2 illustrates typical connections
between independent host systems and corresponding
CYP15G0403DXB chips
As a second-generation HOTLink device, the
CYP15G0403DXB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, command, and BIST) with other
HOTLink devices. The transmit (TX) section of the
CYP15G0403DXB Quad HOTLink II consists of four
independent byte-wide channels. Each channel can accept
either 8-bit data characters or preencoded 10-bit transmission
characters. Data characters may be passed from the Transmit
Input Register to an integrated 8B/10B Encoder to improve
their serial transmission characteristics. These encoded
characters are then serialized and output from dual Positive
ECL (PECL) compatible differential transmission-line drivers
at a bit-rate of either 10 or 20 times the input reference clock
for that channel.
.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-02065 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 10, 2011