CY7C68003_10 Datasheet, PDF (12/27 Pages) Cypress Semiconductor – MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver

CY7C68003
CLOCK
Figure 10. USB Receive While DIR is Previously High
DATA[7:0]
Previous
RX CMD
(RxActive)
RX CMD
PID
D1
RX CMD
D2
DIR
STP
D3
Turn around
NXT
Immediate Register Read and Write
An immediate register is accessed by sending the TX CMD byte first (see Figure 11 and Figure 12 on page 13). This byte is sent as
a regread or regwrite command, depending on the intended operation.
For a register write (see Figure 11), the link first sends a register write TX CMD byte and waits for NXT to assert. After NXT asserts,
the link sends the register write data and waits for NXT to assert again. After the second assertion is detected, the link asserts STP
in the following cycle to complete the operation. The TX2UL detects this STP assertion before it can accept another transmit command.
If the TX2UL aborts rewrite by asserting DIR, the link repeats the entire process again when the bus is idle.
For a register read (see Figure 12 on page 13), the link sends a register read command and waits for NXT to assert. In the cycle after
NXT asserts, the TX2UL asserts DIR to gain control of the data bus. In the cycle, after DIR asserts the TX2UL returns the register
read data. The TX2UL does not assert NXT when DIR is asserted during the register read operation, even during the cycle when the
register read data is returned. If the TX2UL aborts the regread by asserting DIR earlier than shown in Figure 12 on page 13, the link
retries the regread when the bus is idle.
Figure 11. Register Write
CLOCK
DATA[7:0]
TX CMD
(RegWrite)
Data
DIR
STP
NXT
Document Number: 001-15775 Rev. *I
Page 12 of 27
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