CY7C008V_12 Datasheet, PDF (12/23 Pages) Cypress Semiconductor – 3.3 V 4 K / 8 K / 16 16 Dual-Port Static RAM

Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing^{[28, 29, 30, 31]}
t_WC
ADDRESS
OE
CE ^[32]
R/W
DATA OUT
DATA IN
t_AW
t_SA
t_PWE^[31]
NOTE 34
t_HZWE^[33]
t_SD
Write Cycle No. 2: CE Controlled Timing^{[28, 29, 30, 35]}
t_WC
ADDRESS
CE ^[32]
t_SA
R/W
t_AW
t_SCE
t_SD
DATA IN
CY7C008V/009V
CY7C018V/019V
t_HZOE^[33]
t_HA
t_LZWE
t_HD
NOTE 34
t_HA
t_HD
Notes
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t_SCE or t_PWE) of a LOW CE or SEM.
30. t_HA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
31.
If OE is LOW during a R/W controlled write cycle, the write
to be placed on the bus for the
as short as the specified t_PWE.
required
t_SD.
If
OE
is
HIGH
pduulrsinegwaidnthRm/Wusctobnetrothlleedlawrgreitreocfytc_{PlWe,Ethoirs(trHeZqWuiEre+mteSnDt)}
to allow the I/O
does not apply
drivers
and the
to turn off and data
write pulse can be
32. To access RAM, CE = V_IL, SEM = V_IH.
33. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document Number: 38-06044 Rev. *E
Page 12 of 23
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