CY7C008V_12 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 3.3 V 4 K / 8 K / 16 16 Dual-Port Static RAM

CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V 64 K/128 K × 8/9
Dual-Port Static RAM
CY7C008V/009V
CY7C018V/019V
3.3 V 64 K/128 K × 8/9
Dual-Port Static RAM
3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 64 K × 8 organization (CY7C008)
■ 128 K × 8 organization (CY7C009)
■ 64 K × 9 organization (CY7C018)
■ 128 K × 9 organization (CY7C019)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 15/20/25 ns
■ Low operating power
❐ Active: I_CC = 115 mA (typical)
❐ Standby: I_SB3 = 10 A (typical)
Logic Block Diagram
R/W_L
CE_0L
CE_1L
OE_L
CE_L
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and industrial temperature ranges
■ Available in 100-pin TQFP
■ Pb-free packages available
CE_R
R/W_R
CE_0R
CE_1R
OE_R
[1]
8/9
I/O_0L–I/O_7/8L
I/O
Control
I/O
Control
8/9
[1]
I/O_0R–I/O_7/8R
[2]
A_0L–A_15/16L
16/17
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
16/17
[2]
A_0R–A_15/16R
[2]
A_0L–A_15/16L
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[3]
INT_L
16/17
Notes
1. I/O₀–I/O₇ for ×8 devices; I/O₀–I/O₈ for ×9 devices.
2. A₀–A₁₅ for 64 K devices; A₀–A₁₆ for 128 K.
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
16/17
[2]
A_0R–A_15/16R
CE_R
OE_R
R/W_R
SEM_R
[3] _BUSYR
INT_R
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06044 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2010
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