CY14B101L Datasheet, PDF (12/18 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) nvSRAM

PRELIMINARY
CY14B101L
Switching Waveforms (continued)
SRAM Write Cycle 1(WE controlled) ^{[22, 23]}
ADDRESS
CE
t_SA
WE
DATA IN
DATA OUT
PREVIOUS DATA
t_WC
t_SCE
t_HA
t_AW
t_PWE
t_HZWE
t_SD
DATA VALID
HIGH IMPEDANCE
t_HD
t_LZWE
SRAM Write Cycle 2 (CE controlled)
ADDRESS
t_SA
CE
WE
DATA IN
DATA OUT
t_WC
t_SCE
t_AW
t_PWE
t_SD
DATA VALID
HIGH IMPEDANCE
t_HA
t_HD
Note
23. CE or WE must be > V_IH during address transitions.
Document #: 001-06400 Rev. *E
Page 12 of 18
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