CY14B101L Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) nvSRAM

PRELIMINARY
CY14B101L
1-Mbit (128K x 8) nvSRAM
Features
• 25 ns, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
• STORE to QuantumTrap^TM nonvolatile elements is initiated
by software, device pin, or Autostore^TM on power down
• RECALL to SRAM initiated by software or power up
• Infinite READ, WRITE, and RECALL cycles
• 10 mA typical I_CC at 200 ns cycle time
• 200,000 STORE cycles to quantum trap
• 20-year data retention @ 55°C
• Single 3V operation +20%, –10%
• Commercial and industrial temperature
• SOIC and SSOP packages
• RoHS compliance
Logic Block Diagram
Functional Description
The Cypress CY14B101L is a fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap technology
producing, the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles; while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations are also
available under software control.
QuantumTrap
V_CC
V_CAP
1024 x 1024
A₅
POWER
A₆
STORE
CONTROL
A₇
A₈
A₉
A ₁₂
STATIC RAM
ARRAY
RECALL
STORE/
RECALL
CONTROL
HSB
A ₁₃
1024 X 1024
A ₁₄
A ₁₅
A ₁₆
SOFTWARE
DETECT
- A₁₅ A₀
DQ ₀
DQ ₁
DQ ₂
DQ ₃
DQ ₄
DQ ₅
DQ ₆
DQ ₇
COLUMN IO
COLUMN DEC
A₀ A₁ A₂ A₃ A₄ A₁₀ A₁₁
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06400 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2007
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