CY8C25122 Datasheet, PDF (111/148 Pages) Cypress Semiconductor – 8-Bit Programmable System-on-Chip (PSoC™) Microcontrollers

Special Features of the CPU
This filter is implemented using a combination of hard-
ware and software resources. Hardware is used to accu-
mulate the high-speed in-coming data while the software
is used to process the lower speed, enhanced resolution
data for output.
Table 90: Decimator/Incremental Control Register
Bit #
POR
Read/Write
Bit Name
7
0
RW
IGEN [3]
6
0
RW
IGEN [2]
5
0
RW
IGEN [1]
4
0
RW
IGEN [0]
3
0
RW
ICCKSEL
2
0
RW
DCol [1]
1
0
RW
DCol [0]
0
0
RW
DCLKSEL
Bit [7:4]: IGEN [3:0] Individual enables for each analog column that gates the Analog Comparator based on the
ICCKSEL input (Bit 3)
Bit 3: ICCKSEL Clock select for Incremental gate function
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Bit [2:1]: DCol [1:0] Selects Analog Column Comparator source
0 0 = Analog Column Comparator 0
0 1 = Analog Column Comparator 1
1 0 = Analog Column Comparator 2
1 1 = Analog Column Comparator 3
Bit 0: DCLKSEL Clock select for Decimator latch
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Decimator Incremental Register (DEC_CR, Address = Bank 0, E6h)
Table 91: Decimator Data High Register
Bit #
POR
Read/Write
Bit Name
7
0
RW
Data [7]
6
0
RW
Data [6]
5
0
RW
Data [5]
4
0
RW
Data [4]
3
0
RW
Data [3]
2
0
RW
Data [2]
1
0
RW
Data [1]
0
0
RW
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the high order byte within the 16-bit decimator data registers
Any 8-bit data value when written will cause both the Decimator Data High (DEC_DH) and Decimator Data Low
(DEC_DL) registers to be cleared
Decimator High Register (DEC_DH / DEC_CL, Address = Bank 0, E4h)
Table 92: Decimator Data Low Register
Bit #
POR
Read/Write
Bit Name
7
0
R
Data [7]
6
0
R
Data [6]
5
0
R
Data [5]
4
0
R
Data [4]
3
0
R
Data [3]
2
0
R
Data [2]
1
0
R
Data [1]
0
0
R
Data [0]
Bit [7:0]: Data [7:0]
8-bit data value when read is the low order byte within the 16 bit decimator data registers
Decimator Data Low Register (DEC_DL, Address = Bank 0, E5h)
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
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