W199 Datasheet, PDF (11/14 Pages) Cypress Semiconductor – Spread Spectrum FTG for VIA Apollo Pro-133

PRELIMINARY
W199
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) (continued)
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adja-
cent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist pri-
or to frequency stabilization.
Z_o
AC Output Impedance Average value during switching transition.
Used for determining series termination
value.
Min.
30
12.0
12.0
1
1
45
1.5
Typ.
30
Max.
4
4
55
250
500
4
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Z_o
Description
Test Condition/Comments
Frequency, Actual
Frequency generated by crystal oscillator
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
Duty Cycle
Measured on rising and falling edge at 1.25V
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
11