W144 Datasheet, PDF (11/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W144
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
t_P
t_H
t_L
t_R
t_F
t_PLH
t_PHL
t_D
t_JC
t_SK
t_O
f_ST
Z_o
Description
Period
High Time
Low Time
Output Rise Edge
Rate
Output Fall Edge
Rate
Prop Delay LH
Prop Delay HL
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
CPU to PCI Clock
Skew
Frequency
Stabilization from
Power-up (cold start)
AC Output
Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V,
at min. edge rate (1.5 V/ns)
Duration of clock cycle below 0.4V,
at min. edge rate (1.5 V/ns)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Input edge rate faster than 1 V/ns
Input edge rate faster than 1 V/ns
Measured on rising and falling
edge at 1.5V, at min. sdge rate
(1.5 V/ns)
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Mea-
sured on rising edge at 1.5V. CPU
leads PCI output.
Assumes full supply voltage
reached within 1 ms from power-
up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching
transition. Used for determining
series termination value.
CPU = 66.6 MHz
Min. Typ. Max.
30
5.6
5.3
1.5
4
1.5
4
1
5
1
5
45
55
250
250
1.5
4
3
30
CPU = 100 MHz
Min. Typ. Max. Unit
30
ns
3.3
ns
3.1
ns
1.5
4 V/ns
1.5
4 V/ns
1
5 ns
1
5 ns
45
55 %
250 ps
250 ps
1.5
4 ns
3 ms
30
Ω
11