W144 Datasheet, PDF (10/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W144
DC Electrical Characteristics: (continued)
T_A = 0°C to +70°C; V_DDQ3 = 3.3V±5%; V_DDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max. Unit
Crystal Oscillator
V_TH
X1 Input threshold Voltage^[5]
C_LOAD
Load Capacitance, Imposed on
External Crystal^[6]
C_IN,X1
X1 Input Capacitance^[7]
Pin Capacitance/Inductance
V_DDQ3 = 3.3V
Pin X2 unconnected
1.65
V
14
pF
28
pF
C_IN
Input Pin Capacitance
Except X1 and X2
5
pF
C_OUT
Output Pin Capacitance
6
pF
L_IN
Input Pin Inductance
7
nH
Notes:
3. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors.
4. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
5. X1 input threshold voltage (typical) is V_DDQ3/2.
6. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
T_A = 0°C to +70°C; V_DDQ3 = 3.3V±5%; V_DDQ2 = 2.5V±5%; f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25
15
15.5 10
10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.6
3.3
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.3
3.1
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1.5
4 1.5
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1.5
4 1.5
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
200
imum difference of cycle time between
two adjacent cycles.
200 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
250
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
250 ps
3 ms
Z_o
AC Output Impedance Average value during switching transi-
20
tion. Used for determining series termi-
nation value.
20
Ω
10