MB15E03SL Datasheet, PDF (11/29 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler

MB15E03SL
Table 5. Prescaler Data Setting
SW
Prescaler Divide Ratio
H
64/65
L
128/129
Table 6. Charge Pump Current Setting
CS
Current Value
H
±6.0 mA
L
±1.5 mA
Table 7. LD/fout Output Select Data Setting
LDS
LD/fOUT Output Signal
H
fout signal
L
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin
(fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is
shown below.
Table 8. FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
DO
φR
φP
LD/fout
DO
φR
φP
fr > fp
H
L
L
L
H
Z*
fr < fp
L
H
Z*
fout = fr
H
L
L
fr = fp
Z*
L
Z*
Z*
L
Z*
* : High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
LD/fout
fout = fp
• When the LPF and VCO characteristics are
similar to (1), set FC bit high.
(1)
• When the VCO characteristics are similar to (2),
set FC bit low.
PLL
LPF
VCO
VCO
Output
Frequency
(2)
LPF Output Voltage
10
DS04–21359–6E