CY7C1364CV33 Datasheet, PDF (11/21 Pages) Cypress Semiconductor – 9-Mbit (256 K × 32) Pipelined Sync SRAM

CY7C1364CV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter ^{[9, 10]}
Description
Test Conditions
Min
I_SB3
Automatic CE Power-Down
V_DD = Max, Device Deselected, 6-ns cycle,
–
Current – CMOS Inputs
V_IN  0.3 V or V_IN > V_DDQ – 0.3 V, 166 MHz
f = f_MAX = 1/t_CYC
I_SB4
Automatic CE Power-down
V_DD = Max, Device Deselected, 6-ns cycle,
–
Current – TTL Inputs
V_IN  V_IH or V_IN  V_IL, f = 0
166 MHz
Max Unit
100
mA
40
mA
Capacitance
Parameter ^[11]
Description
C_IN
C_CLK
C_I/O
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
Parameter ^[11]
Description
_JA
Thermal Resistance
(Junction to Ambient)
_JC
Thermal Resistance
(Junction to Case)
Test Conditions
T_A = 25 °C, f = 1 MHz, V_DD = 3.3 V, V_DDQ = 2.5 V
100-pin TQFP
Max.
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
29.41
6.13
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z₀ = 50
3.3V
OUTPUT
R_L = 50
5 pF
V_T = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
2.5V
Z₀ = 50
OUTPUT
R_L = 50
5 pF
V_T = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
R = 317
R = 351
V_DDQ
GND
ALL INPUT PULSES
10%
90%
 1 ns
90%
10%
 1 ns
(b)
(c)
R = 1667
R =1538
V_DDQ
GND
ALL INPUT PULSES
10%
90%
 1 ns
90%
10%
 1 ns
(b)
(c)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74576 Rev. *B
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