CY7C1364CV33 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 9-Mbit (256 K × 32) Pipelined Sync SRAM

CY7C1364CV33
9-Mbit (256 K × 32) Pipelined Sync SRAM
9-Mbit (256 K × 32) Pipelined Sync SRAM
Features
■ Registered inputs and outputs for pipelined operation
■ 256 K × 32 common I/O architecture
■ 3.3 V core power supply (V_DD)
■ 2.5 V/3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 3.5 ns (for 166-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in JEDEC-standard lead-free 100-pin TQFP package
■ TQFP Available with 3-Chip Enable
■ “ZZ” Sleep Mode Option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Functional Description
The CY7C1364CV33 SRAM integrates 256 K × 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered Clock
Input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining Chip Enable (CE₁),
depth-expansion Chip Enables (CE₂ and CE₃), Burst Control
inputs (ADSC, ADSP, and ADV), Write Enables (BW_[A:D], and
BWE), and Global Write (GW). Asynchronous inputs include the
Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the Byte Write control inputs. GW when active _LOW causes
all bytes to be written.
The CY7C1364CV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
166 MHz Unit
3.5
ns
180
mA
40
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-74576 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 1, 2012